Mar. 2006

Objective: Test Engineering Position

A challenging assignment in the field of Electronic Hardware Test Engineering, design verification test, characterization, analysis, etc.

Summary of Skills:

Digital & Mixed Signal VLSI characterization & production tests. VLSI, In-circuit, and functional board ATE test development. PC based test systems. VLSI Design verification and debug. System diagnostic programming. Test plans. Image Sensor test. Automatic wafer probing and package handler experience.

Digital circuit design. Computer I/O sub-system designs. Analog and opto- electronic VLSI design. Analog and Digital Circuit simulation. PCB design.

Visual C++ & C programming. Unix Shell scripting. Microsoft Word and Excel. System administration: Solaris, HP-UX, Windows 2003/XP/NT/98, Linux. EDA tool support. Linux video card driver development. Scientific applications programming. Assembly language programming for hardware debugging.


Career Summary:


Design Verification Test Engineer, since May 2003 Storage Area Network Host Bus Adapters, ASICs, and other SAN components.


Test Engineer – CMOS Image Sensors. Dec. 1999 to Jan. 2002 Image Sensor test and characterization.


Senior Systems Engineer. Oct. 1996 to Oct. 1999. Performed several functions in this spin-off startup company from JPL.

Jet Propulsion Laboratory:

Concurrent Processing Devices Group. 1986-96. Analog Neural Network Research.

TRW LSI Products Division:

Test Engineer and CAE systems engineer. 1981-85 ATE programming and test development for VLSI DSP circuits.

Executone Information Systems:

Test Engineering Supervisor. 1980

National Semiconductor, Systems Division:

Test Engineer. 1979

NCR, San Diego:

Logic Design & Diagnostic Programming. 1977-78

Logicon, Military Systems Division:

Logic design. 1975-76




San Diego State University 1979. GPA 4.0

BS in Applied Physics and Information Science

University of California at San Diego 1974.

Publications & Patent:

32 x 32 Peak Detector Array for Optical Correlator Systems

H. Langenbacher, T. Chao, T. Shaw, and J. Yu; Proceedings of the SPIE ‘91 International Symposium on Optical Applied Science and Engineering, San Diego, CA July 1991.

64 x 64 Thresholding Photodetector Array for Optical Pattern Recognition

Harry Langenbacher, Tien-Hsin Chao, Timothy Shaw, and Jeffrey W. Yu ; Proceedings of SPIE -- Volume 1959 Optical Pattern Recognition IV, David P. Casasent, Editor, October 1993

Analog VLSI Neural Network Building Block Chips for Hardware-in-the-loop Learning

T. Duong, T. Brown, M. Tran, H. Langenbacher, and T. Daud; accepted for presentation at the IJCNN 92, at Beijing, China; November 1992.

CMOS Active Pixel Sensor Array With Intensity Driven Readout

H. Langenbacher, S. Kemeny, E. Fossum; JPL/Caltech New Technology Report # 19539/9145, 1994

Radiation Behavior of Analog Neural Network Chip

Harry Langenbacher, Frank Zee, Taher Daud, Anil Thakoor; Proceedings of the 1996 IEEE International Conference on Neural Networks.

A/D Converter Correction Scheme Patent 1998.

Linearity improvement for multiple converters on a single chip.

Boolean Minimization for Large Programmable Logic Arrays

Master’s thesis at San Diego, State University, 1979.

Personal Data:

U.S. citizen.

Secret clearance expired 1995.

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