A challenging assignment in the field of Electronic Hardware Test Engineering, design verification test, characterization, analysis, etc.
Digital & Mixed Signal VLSI characterization & production tests. VLSI, In-circuit, and functional board ATE test development. PC based test systems. VLSI Design verification and debug. System diagnostic programming. Test plans. Image Sensor test. Automatic wafer probing and package handler experience.
Digital circuit design. Computer I/O sub-system designs. Analog and opto- electronic VLSI design. Analog and Digital Circuit simulation. PCB design.
Visual C++ & C programming. Unix Shell scripting. Microsoft Word and Excel. System administration: Solaris, HP-UX, Windows 2003/XP/NT/98, Linux. EDA tool support. Linux video card driver development. Scientific applications programming. Assembly language programming for hardware debugging.
Design Verification Test Engineer, since May 2003 Storage Area Network Host Bus Adapters, ASICs, and other SAN components.
- Improved testing methods and wrote test automation scripts.
- Supporting ASIC and board design engineers in characterization and debugging of new products.
- Using Labview based control system for 4-corner testing.
Test Engineer – CMOS Image Sensors. Dec. 1999 to Jan. 2002 Image Sensor test and characterization.
- HP-94000 ATE programming using C programming under Unix, and C++ programming under Windows for the Image Processing module.
- Wrote production tests for wafer probe and packaged ICs.
- Initiated development of new image quality analysis methods.
- Improvement of test speed and quality resulting in test cost savings and yield improvement.
- Initiated development of ‘light source’ modifications and improvements for image sensor test.
- Worked closely with image sensor design engineers and Product Engineers for resolution of problems.
- Support of production test on-site and off-shore.
- Trained test floor technicians and operators and wrote procedures for calibration and alignment of the light source.
- Performed ‘Pixel Processor’ ASIC design verification and debug, including debug of USB and I2C circuits, by writing C programs and using bench top test equipment, and working with ASIC design engineers.
Senior Systems Engineer. Oct. 1996 to Oct. 1999. Performed several functions in this spin-off startup company from JPL.
- Performed initial development of test requirements and procedures for CMOS image sensor characterization and production.
- Responsible for specification and selection of VLSI test equipment.
- Wrote the first HP 94000 ATE programs for images sensor test.
- Hired two new ATE programmers.
- Participated in development and implementation of PC based test system development with frame-grabber, A/D, D/A, digital I/O boards and Visual C++ programs for use in production test.
- Recruited support personnel for IT department.
- Led the System Administration and CAE tool support for VLSI design engineers for Solaris, HP-UX, and Windows NT computer systems.
- Invented an “A/D Converter Correction Scheme” for use in ASIC designs like image sensors.
Jet Propulsion Laboratory:
Concurrent Processing Devices Group. 1986-96. Analog Neural Network Research.
- Performed design, simulation, and test of various analog, digital, and opto-electronic VLSI circuits.
- Performed I/O system design including VME and ISA board designs for debug, test, and demonstration of parallel processing hybrid VLSI prototype chips.
- Participated in design of a space flight experiment involving our neural network VLSI hardware.
- VLSI design and fabrication through MOSIS.
- Wrote simulation programs for a research project for improvement of star tracking systems.
- Performed the Unix System administration for my department.
TRW LSI Products Division:
Test Engineer and CAE systems engineer. 1981-85 ATE programming and test development for VLSI DSP circuits.
- VLSI characterization program development and testing.
- Wrote ATE programs for wafer probe and package test.
- Supported product engineers for on-site production test.
- As a CAE engineer, wrote software and did VLSI circuit modeling and simulation with HSPICE and SILOS, in support of VLSI design team.
- Led VAX/VMS and Mentor Graphics computer system administration.
Executone Information Systems:
Test Engineering Supervisor. 1980
- Developed initial production test requirements and ATE solution at this startup site for telephone and communication systems manufacturing.
- Responsible for selection and programming of an in-circuit ATE system, and test fixture design and procurement.
- Created a telephone system bench test system for production floor final test. I developed manufacturing test flow and procedures, and trained production test operators and repair technicians.
National Semiconductor, Systems Division:
Test Engineer. 1979
- Wrote ‘functional test’ programs for ATE testing of large computer boards.
- Performed ASIC logic simulation, design verification, and test generation.
- Conducted test vector development and ‘fault simulation’ to support design engineers requirements, and for use in production test.
NCR, San Diego:
Logic Design & Diagnostic Programming. 1977-78
- Completely designed and debugged a micro-programmed, peripheral interface sub-system for an NCR mainframe computer by myself.
- Took over development and debug of a second interface system on the same project for a bank check sorter controller.
- As a diagnostic programmer, developed and assembly language memory test, and a disk interface test for factory testing of mainframe computers.
- Support of factory test technicians for mainframe computer system testing.
Logicon, Military Systems Division:
Logic design. 1975-76
- Assisted in design and debug of high speed computer-to-computer interface boards with TTL and ECL components, doing logic design, assembly and debug of prototype hardware for a military flight simulator.
- Wrote assembly language programs for my own use in prototype hardware test and debug.
San Diego State University 1979. GPA 4.0
BS in Applied Physics and Information Science
University of California at San Diego 1974.
32 x 32 Peak Detector Array for Optical Correlator Systems
H. Langenbacher, T. Chao, T. Shaw, and J. Yu; Proceedings of the SPIE ‘91 International Symposium on Optical Applied Science and Engineering, San Diego, CA July 1991.
64 x 64 Thresholding Photodetector Array for Optical Pattern Recognition
Harry Langenbacher, Tien-Hsin Chao, Timothy Shaw, and Jeffrey W. Yu ; Proceedings of SPIE -- Volume 1959 Optical Pattern Recognition IV, David P. Casasent, Editor, October 1993
Analog VLSI Neural Network Building Block Chips for Hardware-in-the-loop Learning
T. Duong, T. Brown, M. Tran, H. Langenbacher, and T. Daud; accepted for presentation at the IJCNN 92, at Beijing, China; November 1992.
CMOS Active Pixel Sensor Array With Intensity Driven Readout
H. Langenbacher, S. Kemeny, E. Fossum; JPL/Caltech New Technology Report # 19539/9145, 1994
Radiation Behavior of Analog Neural Network Chip
Harry Langenbacher, Frank Zee, Taher Daud, Anil Thakoor; Proceedings of the 1996 IEEE International Conference on Neural Networks.
A/D Converter Correction Scheme Patent 1998.
Linearity improvement for multiple converters on a single chip.
Boolean Minimization for Large Programmable Logic Arrays
Master’s thesis at San Diego, State University, 1979.
Secret clearance expired 1995.
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